A solid-state transformer is one of the most consequential devices in the grid's future — a power-electronic replacement for the century-old iron-and-copper transformer. So US12500415B1, granted to Sandia National Laboratories on December 16, 2025, is worth reading carefully, and claim 1 is narrower than "solid-state transformer" would suggest.
The load-bearing limitation is common-mode insult mitigation. Common-mode disturbances — voltages or currents that appear together on all conductors relative to ground — are a known hazard in power electronics, causing interference and stressing insulation. Claim 1 fences a way to mitigate them within an SST. The CPC tags (H02M 3/33573 isolated DC-DC, H02M 7/537 inversion, H02J 3/001 network circuit arrangements) place it in the SST's internal converter stages.
This is, by construction, a strong narrow claim. The SST architecture itself has extensive prior art; claiming the whole device would fail. Claiming a specific, real protection problem — common-mode insults — and a method to handle it is novel, defensible, and hard to design around because the problem is unavoidable. Every SST has to deal with common-mode effects somehow.
Contrast it with the broad SST publications in the same period (a 2025 US20250279730A1 simply titled "Solid-State Transformer," and Hitachi's US12244218B2 on a power-grid SST). Those stake architecture; Sandia stakes a protection mechanism. The narrow claim is often the more enforceable one.
The lab-IP caution applies: Sandia does not deploy grids, so this is research IP destined for licensing, not a product. But the SST is widely expected to become a backbone device for high-penetration renewable distribution, and national-lab IP on its failure modes is exactly the foundational work that the eventual commercial devices will have to license or design around. A late-2025 Sandia grant is an early stake in that ground.